EPM7128STC100-15N

Programmable Logic Device Family

Rated 5 Rating 5 | reviews | Write a review

Price:: US $14.00~18.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
1 ~ 10 :	18.00 / Piece
50 ~ 100 :	15.00 / Piece
1000 ~ 5000 :	14.00 / Piece

PartNumber:: EPM7128STC100-15N

Brand:: Altera Corporation - ALTR | Pack: TQFP | D/C: 11+

Availability:: Supply Ability: 5000/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Not exactly what you want? Post a quick Buying Request!

Sold By

Ms. Kaisy's store

(China (Mainland))

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2013-03-04

From Other Seller

Part Number:EPM7128STC100-15N
US $14.00 - 18.00
Programmable Logic Device Family EPM7128STC100-15N

US $2.95 - 3.28 / Piece
(0) Remove
Quantity:

piece

Product Summary

The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture.

Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP,

pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed

grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special

Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2

Parametrics

Absolute Maximum Ratings:

VCC, Supply voltage, With respect to ground:-2.0V to 7.0 V
V, DC input voltage:-2.0V to 7.0 V
IOUT, DC output current, per pin: -25mA to 25 mA
TSTG, Storage temperature, No bias:-65℃ to 150℃
TAMB, Ambient temperature, Under bias:-65℃ to 135℃
TJ,Junction temperature, Ceramic packages, under bias: 150℃;PQFP and RQFP packages, under bias :135℃

Features

1.High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX architecture
2.5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
3.Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
4. Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
5.Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates
6.5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
7.PCI-compliant devices available